Code For Half Adder In Verilog (Modelsim)

Code :-

module ha(sum,cout,a,b);

input a,b;

output sum,cout;

xor a1(sum,a,b);

and a2(cout,a,b);

endmodule

module test_ha;

reg a,b;

wire sum,cout;

ha h1(sum,cout,a,b);

initial

begin

a=0;b=0;

#10 a=1;b=0;

#10 a=0;b=1;

#10 a=1;b=1;

end

endmodule

Output :-