Code For Full Adder In Verilog (Modelsim)

Code : -

module fa(sum,cout,a,b,c);

input a,b,c;

output sum,cout;

xor h1(w0,a,b);

xor h2(sum,w0,c);

and h3(w1,a,b);

and h4(w2,w0,c);

or h5(cout,w2,w1);

endmodule

module tb_fa;

reg a,b,c;

wire sum , cout;

fa x1(sum,cout,a,b,c);

initial

begin

a=0;b=0;c=0;

#10 a=0;b=0;c=1;

#10 a=0;b=1;c=0;

#10 a=0;b=1;c=1;

#10 a=1;b=0;c=0;

#10 a=1;b=0;c=1;

#10 a=1;b=1;c=0;

#10 a=1;b=1;c=1;

end 

endmodule

Output : -

Circuit Diagram : -